Example embodiments of the inventive concepts herein relate to a phase locked loop circuit, and more particularly, to a phase locked loop circuit using an analog-digital mixed filter.
When a signal is represented in a frequency domain, the signal is divided into a magnitude component indicating signal strength and a phase component indicating time characteristics. The phase component of the signal is easily changed since it is sensitive to an influence of a temperature or a peripheral circuit. For example, when a digital signal is transmitted, a signal delay may occur in a clock signal according to a signal path. When the signal delay occurs, a phase of the signal is changed. Therefore, a circuit may be required to perform synchronization on a phase of a clock signal.
A phase locked loop (PLL) circuit is a frequency feedback circuit stably outputting a certain frequency signal which is synchronized with a frequency of a signal input externally. The PLL circuit is widely used for analog or digital electronic circuit systems. For example, the PLL circuit may be used for stably providing an oscillating frequency of a local oscillation circuit in order to transmit and receive a signal in a wireless communication system, or for generating a stable reference clock signal required in digital signal processing of a digital circuit such as a microprocessor.
Recently, as a semiconductor integration technology is developed, a PLL circuit having a small area may be desired to be able to be included in a semiconductor chip. Accordingly, an all-digital phase locked loop is provided on the basis of a digital controlled oscillator operating in a digital scheme. However, since the digital controlled oscillator is sensitive to process, voltage, and temperature (PVT) variations, it becomes difficult to precisely control the PLL circuit, as a size of a semiconductor chip gets smaller.